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Madushan
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Posts by Madushan
Implementation of Transmission Control Protocol in FPGA
33 months ago
by Madushan
in Verilog Projects
In this project, Implementation of Transmission Control Protocol is carried out in Xilinx XUPV5-LX110T Evaluation Platform. But the implementation can be easily modified to work with any FPGA with adequate amount of Block RAM support.
Transmission Control Protocol is the protocol responsible for maintaining the reliability (guaranteed transmission of data segments) of the end to end network/internet connections. It’s a connection oriented protocol which process the incoming and outgoing packets based on its respective connection which makes this protocol complex compared to the other TCP/IP stack protocols. TCP is also a stream oriented protocol which guarantees the received sequence of data bytes are exactly in order as transmitted. With the combination of these properties, TCP functions as an agent with inherent intelligence.
As per our project to implement TCP, the goal is to fully implement this protocol in FPGA in contrast to other solutions provided by NIC (Network Interface Card) developers which are basically TOEs (TCP Offload Engines). These TCP Offload Engines implement TCP’s process intensive functions like checksum calculations and handle large segments’ offloads. Some high end Ethernet hardware also implement large receive offload and TCP acknowledgement offload. But none of these solutions fully implement the TCP protocol in hardware.
The advantages of fully implementing TCP protocol in hardware are very high. For example, to process full duplex gigabit data link in software, it utilizes over 80% of a 2.4GHz Pentium 4 processor continuously. This can be completely removed by fully hardware implementing TCP. Apart from the processing time, the processor has to respond to huge number of interrupts to facilitate the acknowledgement generation and other tiny processes of TCP. Apart from those drawbacks, the PCI interface which usually acts as the standard data transferring interface between the computer processor and the NIC is very inefficient when it comes to transferring very small data segments like TCP headers. These problems will be completely removed if the whole TCP is implemented in a separate hardware.
Verilog LCD Controller Module
61 year ago
by Madushan
in Driver Modules
Hi guys,
Thought of presenting you some interesting stuff. A Verilog character LCD Module…. Okey. You know it’s kinda cool to display characters on your FPGA board’s LCD display rather than always lighting LED s to demonstrate your program output. But using these LCDs aren’t easy as using a DOS prompt (CLI) to show a message using a high level software development language. It takes a fair amount of time to figure out how these things work. So it’s much easy, if you have a sample code. Here I’m going to present you a code developed by my friend Geoff. Even though it is written for a Spartan 3E 1600E FPGA board’s character LCD (16×2), you can customize this code easily for any other LCD because the code is quite simple and clear. Having the code alone doesn’t make any sense to you, you should first understand how these character LCDs work. Also it is very important for you to understand about how to write a Verilog LCD module from the beginning. So then the process of editing this sample code becomes very easy. So please follow the steps.
Module Specs :
Originally written for : Spartan 3E 1600E FPGA development board (but easily configurable with any other board).
LCD Display Controller : Sitronix ST7066U
FPGA to LCD Controller interface type : 8 bit interface
LCD Display size : 16×2
link : Download Verilog Character LCD Driver Module
If you are new to the topic please follow the rest of the article.
Installing a verilog design in a FPGA using ISE Design Suit
2Hi guys,
My earlier post (Getting started with Verilog) gave you some information about how to start learning Verilog HDL. Now reading tutorials and books alone doesn’t help you much. You really need to do some practicals. So in this post I’m gonna help you with “how to start to write verilog programs using ISE Design Suit? and how to install a Verilog program in a FPGA?”. Before starting, let me get this straight. Here the software that you need to use is ISE Design Suit, which is a product of Xilinx Inc and this software can only be used if you are using a FPGA which is developed by Xilinx. Ex: – Spartan boards, Virtex boards, etc. Please download ISE and get the web pack license, its free and enough for most of the projects that we can do with FPGAs. If you have a FPGA board developed by Altera, then you have to use their software named “Quartus”.
Getting started with verilog HDL
11Hi Guys,
Thought of starting a blog to help the newbies about verilog HDL. BTW I’m a newbie too… I’ve been learning verilog for 1 or 2 months now. One thing that I have to say is learning verilog is full of fun !!! Really … But have to tell you, it is not easy as high level programming languages like java or C++. But when you get used to it its syntax, it’s easy. One thing that you have to always bear in mind when writing HDL codes is that, you are actually arranging hardware elements for a circuit (inside the FPGAs) rather than providing some instruction set to run on top of hardware like in other programming languages (C, C++, C#.net or even assembly language)…
One thing I realized is that when you are working with Verilog for sometime, you forget that this is a HDL (Hardware Definition Language) and you’ll try to do everything you can do with other high level languages. It may be the syntax of Verilog you know. Its syntax has similarities with vb.net and C. BTW don’t get confuse VHDL with Verilog HDL. VHDL is also another hardware definition language.