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	<title>Comments for HDL Geek</title>
	<atom:link href="http://ex-geek.com/comments/feed/" rel="self" type="application/rss+xml" />
	<link>http://ex-geek.com</link>
	<description>Digital Design Blog ...</description>
	<lastBuildDate>Wed, 18 Apr 2012 19:27:50 +0000</lastBuildDate>
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		<title>Comment on Verilog LCD Controller Module by Ammad Ali</title>
		<link>http://ex-geek.com/verilog-lcd-controller-module/#comment-35</link>
		<dc:creator>Ammad Ali</dc:creator>
		<pubDate>Wed, 18 Apr 2012 19:27:50 +0000</pubDate>
		<guid isPermaLink="false">http://www.verilog.asia/?p=70#comment-35</guid>
		<description>very informative,,,,</description>
		<content:encoded><![CDATA[<p>very informative,,,,</p>
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	<item>
		<title>Comment on Implementation of Transmission Control Protocol in FPGA by Madushan</title>
		<link>http://ex-geek.com/implementation-of-transmission-control-protocol-in-fpga/#comment-34</link>
		<dc:creator>Madushan</dc:creator>
		<pubDate>Fri, 13 Apr 2012 09:07:35 +0000</pubDate>
		<guid isPermaLink="false">http://www.verilog.asia/?p=110#comment-34</guid>
		<description>Sorry buddy, I was a little busy and the PCI part was done by another group member of our team, and he used a software called WinDriver from Jungo to communicate with the PCI core (generated from xilinx IP Cores). http://www.jungo.com/st/windriver_usb_pci_driver_development_software.html. Hope this helps, good luck with your project and let me know if you have anything else. Thanks</description>
		<content:encoded><![CDATA[<p>Sorry buddy, I was a little busy and the PCI part was done by another group member of our team, and he used a software called WinDriver from Jungo to communicate with the PCI core (generated from xilinx IP Cores). <a href="http://www.jungo.com/st/windriver_usb_pci_driver_development_software.html" rel="nofollow">http://www.jungo.com/st/windriver_usb_pci_driver_development_software.html</a>. Hope this helps, good luck with your project and let me know if you have anything else. Thanks</p>
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	<item>
		<title>Comment on Implementation of Transmission Control Protocol in FPGA by John</title>
		<link>http://ex-geek.com/implementation-of-transmission-control-protocol-in-fpga/#comment-33</link>
		<dc:creator>John</dc:creator>
		<pubDate>Mon, 09 Apr 2012 18:46:20 +0000</pubDate>
		<guid isPermaLink="false">http://www.verilog.asia/?p=110#comment-33</guid>
		<description>Good work buddy!! Even am trying to build xupv5-lx110t xilinx as an intelligent  NIC with added features. It would be of great help if you could shed some light on how you proceded with the implementation on the virtex 5, especially on the PCIe interfacing. Any documents/links would be of great help. Awaiting your response. Thanks in advance.</description>
		<content:encoded><![CDATA[<p>Good work buddy!! Even am trying to build xupv5-lx110t xilinx as an intelligent  NIC with added features. It would be of great help if you could shed some light on how you proceded with the implementation on the virtex 5, especially on the PCIe interfacing. Any documents/links would be of great help. Awaiting your response. Thanks in advance.</p>
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	</item>
	<item>
		<title>Comment on Verilog LCD Controller Module by an</title>
		<link>http://ex-geek.com/verilog-lcd-controller-module/#comment-25</link>
		<dc:creator>an</dc:creator>
		<pubDate>Thu, 16 Feb 2012 21:10:50 +0000</pubDate>
		<guid isPermaLink="false">http://www.verilog.asia/?p=70#comment-25</guid>
		<description>Amazing post. Thanks for taking the time to write it. REALLY appreciate it =D</description>
		<content:encoded><![CDATA[<p>Amazing post. Thanks for taking the time to write it. REALLY appreciate it =D</p>
]]></content:encoded>
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	<item>
		<title>Comment on Getting started with verilog HDL by Sang Cobbin</title>
		<link>http://ex-geek.com/getting-started-with-verilog/#comment-23</link>
		<dc:creator>Sang Cobbin</dc:creator>
		<pubDate>Thu, 19 Jan 2012 13:54:39 +0000</pubDate>
		<guid isPermaLink="false">http://lkmadushan.wordpress.com/?p=11#comment-23</guid>
		<description>I like this site very much so much good info.</description>
		<content:encoded><![CDATA[<p>I like this site very much so much good info.</p>
]]></content:encoded>
	</item>
	<item>
		<title>Comment on Getting started with verilog HDL by Levitra</title>
		<link>http://ex-geek.com/getting-started-with-verilog/#comment-22</link>
		<dc:creator>Levitra</dc:creator>
		<pubDate>Sun, 15 Jan 2012 07:13:59 +0000</pubDate>
		<guid isPermaLink="false">http://lkmadushan.wordpress.com/?p=11#comment-22</guid>
		<description>Thank you for posting this. I fully agree with your opinion.</description>
		<content:encoded><![CDATA[<p>Thank you for posting this. I fully agree with your opinion.</p>
]]></content:encoded>
	</item>
	<item>
		<title>Comment on Verilog LCD Controller Module by AB</title>
		<link>http://ex-geek.com/verilog-lcd-controller-module/#comment-21</link>
		<dc:creator>AB</dc:creator>
		<pubDate>Sat, 14 Jan 2012 16:51:59 +0000</pubDate>
		<guid isPermaLink="false">http://www.verilog.asia/?p=70#comment-21</guid>
		<description>excellent knowledge about lcd of fpga</description>
		<content:encoded><![CDATA[<p>excellent knowledge about lcd of fpga</p>
]]></content:encoded>
	</item>
	<item>
		<title>Comment on Implementation of Transmission Control Protocol in FPGA by Madushan</title>
		<link>http://ex-geek.com/implementation-of-transmission-control-protocol-in-fpga/#comment-19</link>
		<dc:creator>Madushan</dc:creator>
		<pubDate>Sat, 31 Dec 2011 02:53:34 +0000</pubDate>
		<guid isPermaLink="false">http://www.verilog.asia/?p=110#comment-19</guid>
		<description>Thanks for taking interest in this subject, I did this using Verilog and it was for one of my university projects. And I&#039;m legally bonded, not to share the code</description>
		<content:encoded><![CDATA[<p>Thanks for taking interest in this subject, I did this using Verilog and it was for one of my university projects. And I&#8217;m legally bonded, not to share the code</p>
]]></content:encoded>
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	<item>
		<title>Comment on Implementation of Transmission Control Protocol in FPGA by RENUKA K L</title>
		<link>http://ex-geek.com/implementation-of-transmission-control-protocol-in-fpga/#comment-18</link>
		<dc:creator>RENUKA K L</dc:creator>
		<pubDate>Tue, 27 Dec 2011 09:27:06 +0000</pubDate>
		<guid isPermaLink="false">http://www.verilog.asia/?p=110#comment-18</guid>
		<description>Implementation of Transmission Control Protocol in FPGA Coding...</description>
		<content:encoded><![CDATA[<p>Implementation of Transmission Control Protocol in FPGA Coding&#8230;</p>
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	<item>
		<title>Comment on Implementation of Transmission Control Protocol in FPGA by RENUKA K L</title>
		<link>http://ex-geek.com/implementation-of-transmission-control-protocol-in-fpga/#comment-17</link>
		<dc:creator>RENUKA K L</dc:creator>
		<pubDate>Tue, 27 Dec 2011 09:26:02 +0000</pubDate>
		<guid isPermaLink="false">http://www.verilog.asia/?p=110#comment-17</guid>
		<description>Pls Get me the implementation of TCP/IP protocol core in VHDL Coding ,,,its for my project purpse........pls do reply</description>
		<content:encoded><![CDATA[<p>Pls Get me the implementation of TCP/IP protocol core in VHDL Coding ,,,its for my project purpse&#8230;&#8230;..pls do reply</p>
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