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	<title>HDL Geek</title>
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	<description>Digital Design Blog ...</description>
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		<title>Implementation of Transmission Control Protocol in FPGA</title>
		<link>http://ex-geek.com/implementation-of-transmission-control-protocol-in-fpga/</link>
		<comments>http://ex-geek.com/implementation-of-transmission-control-protocol-in-fpga/#comments</comments>
		<pubDate>Tue, 22 Nov 2011 02:16:05 +0000</pubDate>
		<dc:creator>Madushan</dc:creator>
				<category><![CDATA[Verilog Projects]]></category>
		<category><![CDATA[FPGA Based TCP Protocol Implementation]]></category>
		<category><![CDATA[Full TCP implementation in FPGA]]></category>
		<category><![CDATA[Hardware implementation of TCP Protocol]]></category>
		<category><![CDATA[Implementation of TCP in FPGA]]></category>
		<category><![CDATA[TCP Full Implementation in Hardware]]></category>
		<category><![CDATA[TCP Protocol Hardware Implementation]]></category>
		<category><![CDATA[TCP Protocol in FPGA]]></category>
		<category><![CDATA[TCP Protocol in Virtex 5]]></category>
		<category><![CDATA[Verilog Implementation of TCP]]></category>
		<category><![CDATA[Verilog Transmission Control Protocol (TCP)]]></category>

		<guid isPermaLink="false">http://www.verilog.asia/?p=110</guid>
		<description><![CDATA[In this project, Implementation of Transmission Control Protocol is carried out in Xilinx XUPV5-LX110T Evaluation Platform. But the implementation can be easily modified to work with any FPGA with adequate amount of Block RAM support.
Transmission Control Protocol is the protocol responsible for  [...]]]></description>
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		<slash:comments>5</slash:comments>
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		<title>Verilog LCD Controller Module</title>
		<link>http://ex-geek.com/verilog-lcd-controller-module/</link>
		<comments>http://ex-geek.com/verilog-lcd-controller-module/#comments</comments>
		<pubDate>Sat, 08 Jan 2011 09:02:31 +0000</pubDate>
		<dc:creator>Madushan</dc:creator>
				<category><![CDATA[Driver Modules]]></category>
		<category><![CDATA[Download Verilog Character LCD Driver Module]]></category>
		<category><![CDATA[Download Verilog LCD Code]]></category>
		<category><![CDATA[Download Verilog LCD Module]]></category>
		<category><![CDATA[Verilog code for lcd]]></category>
		<category><![CDATA[Verilog LCD Controller]]></category>
		<category><![CDATA[Verilog LCD Module]]></category>

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		<description><![CDATA[Hi guys,
Thought of presenting you some interesting stuff. A Verilog character LCD Module&#8230;. Okey. You know it&#8217;s kinda cool to display characters on your FPGA board&#8217;s LCD display rather than always lighting LED s to demonstrate your program output. But using these LCDs aren&#8217;t easy as using a DOS  [...]]]></description>
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		<slash:comments>7</slash:comments>
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		<item>
		<title>Installing a verilog design in a FPGA using ISE Design Suit</title>
		<link>http://ex-geek.com/installing-a-verilog-design-in-a-fpga-using-ise-design-suit/</link>
		<comments>http://ex-geek.com/installing-a-verilog-design-in-a-fpga-using-ise-design-suit/#comments</comments>
		<pubDate>Thu, 30 Dec 2010 13:09:46 +0000</pubDate>
		<dc:creator>Madushan</dc:creator>
				<category><![CDATA[Verilog]]></category>
		<category><![CDATA[How to program Spartan FPGAs using ISE Webpack]]></category>
		<category><![CDATA[How to start writing verilog programs]]></category>
		<category><![CDATA[How to use ISE Impact]]></category>
		<category><![CDATA[Install .bit file in multiple PROMs in FPGA]]></category>
		<category><![CDATA[Installing a verilog design in a FPGA]]></category>
		<category><![CDATA[ISE doesn't list my FPGA]]></category>
		<category><![CDATA[Using ISE Project Navigator]]></category>
		<category><![CDATA[Using ISE Webpack to program FPGAs]]></category>
		<category><![CDATA[Using USB-based JTAG programming interface]]></category>

		<guid isPermaLink="false">http://lkmadushan.wordpress.com/?p=25</guid>
		<description><![CDATA[Hi guys,
My earlier post (Getting started with Verilog) gave you some information about how to start learning Verilog HDL. Now reading tutorials and books alone doesn&#8217;t help you much. You really need to do some practicals. So in this post I&#8217;m gonna help you with &#8220;how to start to write verilog  [...]]]></description>
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		<slash:comments>2</slash:comments>
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		<title>Getting started with verilog HDL</title>
		<link>http://ex-geek.com/getting-started-with-verilog/</link>
		<comments>http://ex-geek.com/getting-started-with-verilog/#comments</comments>
		<pubDate>Tue, 28 Dec 2010 17:58:04 +0000</pubDate>
		<dc:creator>Madushan</dc:creator>
				<category><![CDATA[Verilog]]></category>
		<category><![CDATA[top sites for verilog]]></category>
		<category><![CDATA[Verilog sample projects]]></category>
		<category><![CDATA[Verilog tutorials]]></category>

		<guid isPermaLink="false">http://lkmadushan.wordpress.com/?p=11</guid>
		<description><![CDATA[Hi Guys,
Thought of starting a blog to help the newbies about verilog HDL. BTW I&#8217;m a newbie too&#8230; I&#8217;ve been learning verilog for 1 or 2 months now. One thing that I have to say is learning verilog is full of fun !!! Really &#8230; But have to tell you, it is not easy as high level programming languages  [...]]]></description>
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		<slash:comments>11</slash:comments>
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