In this project, Implementation of Transmission Control Protocol is carried out in Xilinx XUPV5-LX110T Evaluation Platform. But the implementation can be easily modified to work with any FPGA with adequate amount of Block RAM support.

Transmission Control Protocol is the protocol responsible for maintaining the reliability (guaranteed transmission of data segments) of the end to end network/internet connections. It’s a connection oriented protocol which process the incoming and outgoing packets based on its respective connection which makes this protocol complex compared to the other TCP/IP stack protocols. TCP is also a stream oriented protocol which guarantees the received sequence of data bytes are exactly in order as transmitted. With the combination of these properties, TCP functions as an agent with inherent intelligence.

As per our project to implement TCP, the goal is to fully implement this protocol in FPGA in contrast to other solutions provided by NIC (Network Interface Card) developers which are basically TOEs (TCP Offload Engines). These TCP Offload Engines implement TCP’s process intensive functions like checksum calculations and handle large segments’ offloads. Some high end Ethernet hardware also implement large receive offload and TCP acknowledgement offload. But none of these solutions fully implement the TCP protocol in hardware.

The advantages of fully implementing TCP protocol in hardware are very high. For example, to process full duplex gigabit data link in software, it utilizes over 80% of a 2.4GHz Pentium 4 processor continuously. This can be completely removed by fully hardware implementing TCP. Apart from the processing time, the processor has to respond to huge number of interrupts to facilitate the acknowledgement generation and other tiny processes of TCP. Apart from those drawbacks, the PCI interface which usually acts as the standard data transferring interface between the computer processor and the NIC is very inefficient when it comes to transferring very small data segments like TCP headers. These problems will be completely removed if the whole TCP is implemented in a separate hardware.

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